1. Technical Field
The present invention relates to a semiconductor device in which a structure for providing electrical connections among a plurality of conductive films has been improved.
2. Background Art
A structure for providing electrical connections among a plurality of conductive layers or films employed in a conventional semiconductor device will first be explained by a SRAM as an illustrative example. In general, a memory cell in the SRAM is composed of six elements in total, which include four elements of N type access transistors Q1 and Q2 and driver transistors Q3 and Q4 and two elements of P type load transistors Q5 and Q6 as shown in FIG. 10. However, in this case, the memory cell increases in size, because the six elements are formed on a substrate. To cope with this situation, the size of the memory cell was reduced by using TFTs as the two P type transistors, forming the four N type elements on the substrate and forming the two P type TFT on the N type elements. As this example, a memory cell is known which has been described in, for example, a Technical Digest xe2x80x9cInternational Electron Devices Meeting 1991xe2x80x9d, p. 481-484.
FIGS. 11 through 13 show memory cell patterns of such a SRAM. FIG. 11 shows the layout of active layers 1a and 1b, an element separation region 12, first polysilicon films 2a through 2d and a second polysilicon film 4 all formed on a semiconductor substrate. Further, shown in FIG. 11 are a first polycontact 3a for connecting the active layer 1b and the first polysilicon film 2c to each other, a first polycontact 3b for connecting the active layer 1a and the first polysilicon film 2d to each other and second polycontacts 5a and 5b for respectively connecting the active layers 1a and 1b to the second polysilicon film 4.
FIG. 12 shows the layout of third polysilicon films 6a and 6b and fourth polysilicon films 8a and 8b. Further, shown in FIG. 12 are a third polycontact 7a for connecting a first polysilicon film 2c and a third polysilicon film 6b to each other, a third polycontact 7b for connecting a first polysilicon film 2d and a third polysilicon film 6a to one another, a fourth polycontact 9a for connecting the third polysilicon film 6b and a fourth polysilicon film 8a to each other, and a fourth polycontact 9b for connecting the third polysilicon film 6a and the fourth polysilicon film 8a to each other.
FIG. 13 shows the layout of metal patterns or interconnections 11a and 11b. Further, shown in FIG. 13 are a metal contact 10a for connecting an active layer 1a and the metal interconnection 11a to one another and a metal contact 10b for connecting an active layer 1b and the metal interconnection 11b to one another.
In these drawings, each of the first polysilicon films 2a through 2d is formed as a gate electrode of a substrate transistor. The second polysilicon film 4 is formed as a GND pattern or interconnection for each memory cell. Each of the third polysilicon films 6a and 6b is formed as a gate electrode of a TFT. Each of the fourth polysilicon films 8a and 8b is formed as a source/drain and channel layer of a TFT. Finally, each of the metal interconnections 11a and 11b is formed as a bit line.
FIG. 14 is a sectional structural view taken along line A-Axe2x80x2 of FIGS. 11 to 13. In the drawing, the same reference numerals as those shown in FIGS. 11 through 13 respectively indicate the same elements of structure as those shown in FIGS. 11 to 13.
Referring also to FIG. 14, the memory cell includes a gate oxide film 13a of a bulk transistor, inter-layer insulating films 13b, 13c and 13e, and a gate oxide film 13d of a TFT. Incidentally, the first polysilicon films 2a through 2d and the second polysilicon film 4 may be polysilicide composed of a combination of polysilicon and a silicide layer without being composed of a single polysilicon layer alone.
A tandem contact structure formed by connecting the first polycontact 3b, the third polycontact 7b and the fourth polycontact 9b among the polycontacts illustrated in FIGS. 11 to 13 is understood as viewed from FIG. 14.
The conventional SRAM cell formed in this way has the following problems.
(1) The many polycontacts such as the first through fourth polycontacts 3a, 3b, 5a, 5b, 7a, 7b, 9a and 9b are required to make contact to respective polysilicon layers. Therefore, a number of polycontact masks, frequent photoengraving and etching process for polycontacts are required, resulting in complex processes.
(2) A method of reducing the number of the polycontact masks, called shared contact structures, is known. FIG. 15 shows a sectional structure thereof. A third polysilicon film 6 provides a polycontact simultaneously with respect to an active layer 1 and a first polysilicon film 2 for forming a gate electrode of a transistor. Thus, a first polycontact becomes unnecessary by forming a third polycontact in a shared structure, so that the number of polycontacts can be reduced by one. In each symmetrical cell of the conventional SRAM, however, the two third polycontacts are necessary within the cell because of its symmetry. Since the shared contact is connected to the two layers (active layer 1 and first polysilicon film 2 in the conventional example), it is necessary to increase the size of the shared contact as compared with that of the normal polycontact from the viewpoint of the need for reliable electrical connection of the shared contact to the respective layers. As a result, a problem arises because the cell size increases.
(3) Further, as examples of a TFT, a bottom gate type TFT in which a gate electrode is provided below a polysilicon film for forming source/drain (S/D) and channel regions, and a top gate type TFT in which a gate electrode is provided above a polysilicon film for forming source/drain (S/D) and channel regions, are known. The cells shown in FIGS. 11 through 14 respectively use the bottom gate type TFT. In general, the top gate type TFT is superior in performance to the bottom gate type TFT. When the top gate type TFT and the shared direct contact structure are adopted, the polysilicon film for the P type source/drain (S/D) region of the TFT is brought into contact with an N type active layer. In general, the connection of an N type active layer to a P type polysilicon film is apt to form a PN junction as compared with an N type polysilicon to the P type polysilicon film. If the PN junction is formed, then a adverse effect is exerted on the operation of each cell. It was therefore difficult to combine the shared direct contact and the top gate type TFT into one. The present invention has been provided to solve the conventional problems referred to above.
According to one aspect of the present invention, a semiconductor device comprises a first conductive film formed on a semiconductor substrate, a second conductive film formed on the first conductive film with a first insulating film interposed between them, a third conductive film formed on the second conductive film with a second insulating film interposed between them. And a columnar connecting portion penetrates at least the second insulating film and the first insulating film from the third conductive film so as to reach the first conductive film and the semiconductor substrate. The second conductive film is brought into contact with the columnar connecting portion at its end surface, and the thickness of the second conductive film is less than that of the third conductive film.
According to another aspect of the present invention, a semiconductor device comprises a first conductive film formed on a semiconductor substrate, a second conductive film formed on the first conductive film with a first insulating film interposed between them, a third conductive film formed on the second conductive film with a second insulating film interposed between them. And a columnar connecting portion penetrates at least the second insulating film and the first insulating film from the third conductive film so as to reach the first conductive film and the semiconductor substrate. The second conductive film is brought into contact with the columnar connecting portion at its end surface, and the thickness of the second insulating film is less than that of the first insulating film.
In another aspect of the present invention, in the semiconductor device, an end of the first conductive film extends toward the columnar connecting portion, and the length of the extended end is equal to or less than one-half the diameter of the columnar connecting portion.
In another aspect of the present invention, in the semiconductor device, the first conductive film is brought into contact with the columnar connecting portion at its end surface.
In another aspect of the present invention, in the semiconductor device, a third insulating film is formed between the semiconductor substrate and the first conductive film. The first conductive film is formed as a gate electrode of a substrate transistor. The second conductive film is formed as a channel conductive layer of a TFT transistor, and the third conductive film is formed as a gate electrode of the TFT transistor.
In another aspect of the present invention, in the semiconductor device, the semiconductor substrate has an N type active layer. And the third conductive film and the columnar connecting portion in contact with the N type active layer are formed of N type polysilicon.
Other features and advantages of the present invention will become more apparent from the following description taken together with the accompanying drawings.